35,137 research outputs found

    Hybridized solid-state qubit in the charge-flux regime

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    Most superconducting qubits operate in a regime dominated by either the electrical charge or the magnetic flux. Here we study an intermediate case: a hybridized charge-flux qubit with a third Josephson junction (JJ) added into the SQUID loop of the Cooper-pair box. This additional JJ allows the optimal design of a low-decoherence qubit. Both charge and flux 1/f1/f noises are considered. Moreover, we show that an efficient quantum measurement of either the current or the charge can be achieved by using different area sizes for the third JJ.Comment: 7 pages, 5 figures. Phys. Rev. B, in pres

    Scalable quantum computing with Josephson charge qubits

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    A goal of quantum information technology is to control the quantum state of a system, including its preparation, manipulation, and measurement. However, scalability to many qubits and controlled connectivity between any selected qubits are two of the major stumbling blocks to achieve quantum computing (QC). Here we propose an experimental method, using Josephson charge qubits, to efficiently solve these two central problems. The proposed QC architecture is scalable since any two charge qubits can be effectively coupled by an experimentally accessible inductance. More importantly, we formulate an efficient and realizable QC scheme that requires only one (instead of two or more) two-bit operation to implement conditional gates.Comment: 4 pages, 2 figure

    Semimetalic graphene in a modulated electric potential

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    The π\pi-electronic structure of graphene in the presence of a modulated electric potential is investigated by the tight-binding model. The low-energy electronic properties are strongly affected by the period and field strength. Such a field could modify the energy dispersions, destroy state degeneracy, and induce band-edge states. It should be noted that a modulated electric potential could make semiconducting graphene semimetallic, and that the onset period of such a transition relies on the field strength. There exist infinite Fermi-momentum states in sharply contrast with two crossing points (Dirac points) for graphene without external fields. The finite density of states (DOS) at the Fermi level means that there are free carriers, and, at the same time, the low DOS spectrum exhibits many prominent peaks, mainly owing to the band-edge states.Comment: 12pages, 5 figure

    Charge echo in a Cooper-pair box

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    A spin-echo-type technique is applied to an artificial two-level system that utilizes charge degree of freedom in a small superconducting electrode. Gate-voltage pulses are used to produce the necessary pulse sequence in order to eliminate the inhomogeneity effect in the time-ensemble measurement and to obtain refocused echo signals. Comparison of the decay time of the observed echo signal with estimated decoherence time suggests that low-frequency energy-level fluctuations due to the 1/f charge noise dominate the dephasing in the system.Comment: 4 pages, 3 figure

    EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

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    At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
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